1. Field of the Invention
The present invention relates to techniques for processing digital signals. In particular, the present invention relates to techniques for saving power in digital signal processing.
2. Description of the Related Art
With the advancements in electrical techniques, mobile electronic devices such as laptops and smart phones are widely developed and available. In order to enhance the mobility of such devices, it is critical for those mobile electronic device manufactures to seek ways to decrease both active and standby power consumption while having richer and diversified functions. Furthermore, as public environmental awareness has been raised in recent years, both stationary and mobile electronic devices are expected to have lower power consumption and higher energy utilization efficiency.
In a wireless communication device, the transceiver is usually the hardware component consuming the most power. FIG. 1(A) illustrates one part of a transmitter for digital quadrature modulation (DQM). According to the selection signal, the multiplexer 10 passes the in-phase signal I or the quadrature-phase signal Q to the digital power amplifier 100. Based on the signal marked as “M” at output of the multiplexer 10, the digital logic circuit 12 generates a plurality of signals to control the AND gates 14. When the clock signal in FIG. 1(A) has a high voltage level or is in an enabling state, the AND gates 14 will pass the output signals from the digital logic circuit 12 to the digital-to-analog converting units 16. On the contrary, when the clock signal has a low voltage level or is in a disabling state, the outputs of all the AND gates 14 will remain at a low voltage level regardless of the signals coming from the digital logic circuit 12.
FIG. 1(B) illustrates a conceptual diagram of one type of digital-to-analog converting unit 16. The switch 16B is controlled by the output signal of the AND gate 14 and is assumed to be an ideal switch where off-state impedance is infinity and there is no parasitic capacitance. When the output of the AND gate 14 has a high voltage level, the switch 16B is turned on, so as to provide a current I flowing through the loading 16A. When the output of the AND gate 14 has a low voltage level, the switch 16B is turned off thereby shutting off the current I. It can be seen that the output signal of the AND gate 14 influences the current I flowing through the loading 16A. Furthermore, the amount of current I flowing through the loading 16A influences the output signal of the digital power amplifier 100.
FIG. 1(C) shows a timing diagram of the aforementioned clock signal, selection signal, and data signal M. The clock signal and selection signal are both square signals with 50% duty cycle. The frequency of the selection signal is twice the frequency of the clock signal. When the selection signal has a high voltage level, the multiplexer 10 outputs the in-phase signal I to the digital power amplifier 100. When the selection signal has a low voltage level, the multiplexer 10 outputs the quadrature-phase signal Q to the digital power amplifier 100. It can be seen from FIG. 1(A) and FIG. 1(C) that during the time period marked as “T”, regardless of the voltage level of signal M, the outputs of the AND gates 14 are all zero. However, the toggling of the selection signal in duration T still leads to signal level changes in the signal M. Hence, even though the output signal of the digital power amplifier 100 is not driven by the signal M in duration T, the digital logic circuit 12 still has activities due to the non-static signal M resulting in unnecessary power consumption. The loading 16A may have capabilities of energy storage and energy dissipation. As a result, the kinetic energy circulation within loading 16A may still be related to signal M during duration T although there is no current I flowing through the switch 16B.